Title :
A 2 V CMOS programmable pipelined digital differential matched filter for DS-CDMA system
Author :
Yen, She-Hwa ; Wang, Chorng-Kuang
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper presents a 2 V DS-CDMA programmable digital matched filter with a differential and pipelined structure. A differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summations (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves hardware and power, but also improves the operation speed, which makes PDDMF more suitable for personal communication at high speed and low power requirements than the conventional approach. The PDDMF, implemented in a 0.6 μm CMOS technology, is clocked at 2.5 MHz and consumes 1.6 mW from a single 2 V power supply
Keywords :
CMOS digital integrated circuits; circuit complexity; code division multiple access; digital filters; high-speed integrated circuits; integrated circuit design; low-power electronics; matched filters; pipeline processing; programmable filters; pseudonoise codes; spread spectrum communication; 0.6 mum; 1.6 mW; 2 V; 2.5 MHz; CMOS programmable pipelined digital differential matched filter; DS-CDMA system; differential pipelined structure; differential pseudo-noise code scheme; high speed; low power requirements; multiplication operations; operation speed; personal communication; power consumption; summation operations; Adders; Bandwidth; CMOS logic circuits; CMOS technology; Clocks; Direct-sequence code-division multiple access; Hardware; Matched filters; Multiaccess communication; Power supplies;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824120
