Title :
Bumpless WOW stacking for large-scale 3D integration
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
Abstract :
Wafer-scale three-dimensional (3D) technologies beyond post-scaling, known as Wafer-on-Wafer (WOW), have been developed for high-density integration. WOW consists of four technology modules: wafer thinning, stacking, through-silicon-via (TSV) interconnects without bump electrode pads, and packaging. All modules are carried out at the wafer scale. No degradation for advanced 35-nm SRAM logic and FRAM devices was observed with ultra-thinning below 10-μm for 300-mm and 200-mm wafers.
Keywords :
integrated circuit packaging; large scale integration; bumpless WOW stacking; large scale 3D integration; packaging; technology modules; through-silicon-via interconnects without bump electrode pads; wafer scale; wafer thinning; wafer-on-wafer; Copper; Investments; Packaging; Silicon; Stacking; Three dimensional displays; Through-silicon vias;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667847
