Bottom-up methodology for test preparation and refinement

Author

Grácio, J.A. ; Bicudo, P.A. ; Rua, N.N. ; Oliveira, A.M. ; Almeida, C.F.B. ; Teixeira, J.P.

Author_Institution

INESC, IST, Lisbon, Portugal

fYear

1989

Firstpage

949

Abstract

A bottom-up testing methodology is used to derive realistic fault lists (at layout level), to refine gate-level test patterns, and to provide accurate test validation (at switch-level), thus making possible the evaluation of the fault coverage of the most likely circuit faults. For this purpose, the developed software tools, which are integrated in the ICD toolbox, are described, and their usefulness is ascertained through several design examples. Interesting spin-offs of the proposed methodology and directions of future work are also described

Keywords

MOS integrated circuits; VLSI; automatic testing; integrated circuit testing; integrated logic circuits; logic testing; production testing; ICD toolbox; accurate test validation; bottom-up testing methodology; circuit faults; design examples; design for testing; fault coverage evaluation; gate level test pattern refining; layout level; realistic fault list derivation; software tool development; software tool usefulness; switch-level; test preparation; test refinement; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Logic design; Logic testing; Production; Refining; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100508

Filename

100508