DocumentCode :
1642869
Title :
Packaging technology for imager using through-hole interconnections in Si substrate
Author :
Hirafune, Sayaka ; Yamamoto, Satoshi ; Wada, Hideyuki ; Okanishi, Katsuhito ; Tomita, Michikazu ; Matsumaru, Kouhei ; Suemasu, Tatsuo
Author_Institution :
Electron Device Lab., Fujikura Ltd., Tokyo, Japan
fYear :
2004
Firstpage :
303
Lastpage :
306
Abstract :
For high-density packaging of ICs or other devices, it is one of the essential technologies to form through-hole interconnections in a Si substrate that electric circuits are built on in advance. We have developed a fabrication technology of wafer-level-packaging (WLP) for imagers, using the through-hole interconnections from the backside of the Si substrate to the top. The package consists of a glass cap protecting an image sensing area on the top side, the through-hole interconnections as leads, the copper re-routing and solder bumps on the backside. All processes of the packaging were done at wafer level. This paper describes the fabrication process and evaluation results of the mechanical and electrical characteristics of the WLP for imagers.
Keywords :
chip scale packaging; elemental semiconductors; image sensors; integrated circuit interconnections; silicon; copper rerouting; electric circuits; electrical characteristics; fabrication technology; glass cap; high-density IC packaging; image sensing area; imager; mechanical characteristics; packaging technology; solder bumps; through-hole interconnections; wafer-level-packaging; Etching; Fabrication; Filling; Glass; Insulation; Integrated circuit interconnections; Metal-insulator structures; Packaging; Protection; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Density Microsystem Design and Packaging and Component Failure Analysis, 2004. HDP '04. Proceeding of the Sixth IEEE CPMT Conference on
Print_ISBN :
0-7803-8620-5
Type :
conf
DOI :
10.1109/HPD.2004.1346716
Filename :
1346716
Link To Document :
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