DocumentCode :
164299
Title :
Hardware event treating in nMPRA
Author :
Moisuc, Elena-Eugenia Ciobanu ; Larionescu, Alexandru-Bogdan ; Gaitan, Vasile Gheorghita
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Stefan cel Mare Univ., Suceava, Romania
fYear :
2014
fDate :
15-17 May 2014
Firstpage :
66
Lastpage :
69
Abstract :
In real-time systems, events treating is one of the most important aspects. There can be time events, watchdog timer events, deadline events, interrupt events, mutex events, and synchronization and inter-task communication events. Since multiple events can occur simultaneously, it is important to find a way to select the order in which the events will be treated. For that, in this paper it is presented a method of global prioritization of the events by category using a hardware prioritization scheme for the n-task Multi Pipeline Register Architecture (nMPRA) and an analysis of how are treated mutex and inter-task communication events in the same architecture.
Keywords :
pipeline processing; global prioritization; hardware event treatment; hardware prioritization scheme; inter-task communication events; n-task multipipeline register architecture; nMPRA; Computer architecture; Hardware; Pipelines; Real-time systems; Registers; Software; Synchronization; Real-time systems; embedded systems; event treating; hardware scheduler; inter-task communication; microprocessors; mutex;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Development and Application Systems (DAS), 2014 International Conference on
Conference_Location :
Suceava
Type :
conf
DOI :
10.1109/DAAS.2014.6842429
Filename :
6842429
Link To Document :
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