Adaptive combinational logic circuits based on intrinsic Evolvable Hardware

Evolvable hardware(EHW) has been proposed as a promising technology for adaptive systems in last few years. However, in practical applications, evolutionary algorithms(EAs) often need numerous generations to search a new solution. In general, a mistaken system is damaged if it cannot restore in time, so the inefficiency problem has become an obstacle of developing adaptive and evolvable hardware. This paper analyzes how those three factors as genotype, algorithm, and methodology affect the efficiency of the EAs, as well as to what extent of their influence respectively, then proposes parallel and recursive decomposition (PRD) as a new decomposition strategy to accelerate the adaptation process from methodology perspective. Finally, some adaptive combination logical circuits are implemented on Xilinx Virtex-II Pro (XC2VP20) FPGA. The results demonstrate that PRD has more improvement on adaptation speed than some previous strategies.