Thermally constrained placement of smart-power IC´s and multi-chip modules

This paper presents an algorithm for thermally constrained placement of integrated circuits and multichip modules. The thermal profile of power dissipating components is calculated in advance using an analytical multi-layer thermal model. The result is stored per component in a thermal matrix and used to compute temperature distributions during placement optimization. Simulated annealing is used as the basic placement algorithm. During each iteration of the placement optimization algorithm, the temperature distribution of the placement is calculated by superposition of the thermal profiles of the individual power dissipating components. This can be done very fast since the thermal profiles are calculated in advance and stored in matrices. Performance degradations introduced by temperature gradients can be computed using the local component temperatures and predetermined sensitivity information. The placement cost-function is designed to keep thermal performance degradation within the circuit specifications and to limit component temperatures within safe operating regions. The effectiveness and efficiency of the algorithm is demonstrated with industrial examples