Reverse engineering as a framework for design verification

Author

Shiran, Yehuda

Author_Institution

SILVAR-LISCO, Menlo Park, CA, USA

fYear

1989

Firstpage

969

Abstract

A new framework is described for layout design verification. The main idea is to extract the netlist from the layout and regenerate the schematic database from this netlist. The usefulness of such a database is described. An algorithm for generating the switch-level schematic diagrams is given. It is superior to previous tools in that it is deterministic (other works use heuristics and therefore cannot handle certain problems), it is fast (others are up to 100 times slower), it is technology independent (others were written for CMOS only), and it can be implemented in an extremely short program (around 1000 lines of C)

Keywords

VLSI; circuit layout CAD; integrated logic circuits; algorithm implementation; database usefulness; deterministic algorithm; fast algorithm; layout design verification; netlist extraction; reverse engineering; schematic database regeneration; short program; switch-level schematic diagram generation algorithm; switch-level schematic diagrams; technology independent; Analytical models; CMOS process; CMOS technology; Clustering algorithms; Databases; Displays; Information analysis; Probes; Reverse engineering; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100513

Filename

100513