Title :
Sub-60 nm physical gate length SOI CMOS
Author :
Yang, I.Y. ; Chen, K. ; Smeys, P. ; Sleight, J. ; Lin, L. ; Leong, M. ; Nowak, E. ; Fung, S. ; Maciejewski, E. ; Varekamp, P. ; Chu, W. ; Park, H. ; Agnello, P. ; Crowder, S. ; Assaderaghi, F. ; Su, L.
Author_Institution :
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of silicon film thickness. A high performance SOI CMOS with well-behaved 52 nm gate length devices is demonstrated.
Keywords :
MOSFET; silicon-on-insulator; 60 nm; NFET device; PFET device; device parasitics; history effect; junction capacitance; partially-depleted SOI CMOS transistor; poly gate length scaling; short-channel effect; silicon film thickness optimization; Boron; CMOS technology; Copper; Design optimization; Dielectric substrates; Implants; Parasitic capacitance; Research and development; Silicon on insulator technology; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824186
