Title :
A novel network on chip architecture - Stargon
Author :
Zhang, Xingxing ; Shi, Zewen ; Quan, Heng ; Zeng, Xiaoyang ; Yu, Zhiyi
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
Network-on-Chip (NoC) is the most promising on-chip-interconnection scheme for multi-core processors. In this paper, we propose a novel NoC architecture called Stargon, which is inspired by the Spidergon. A simulation model has been developed to evaluate our architecture. We study the effect of the number of nodes, buffer depth and message length on the performance, and shows that at any situation Stargon is twice of performance compared with Spidergon.
Keywords :
integrated circuit interconnections; microprocessor chips; network-on-chip; Spidergon; Stargon; buffer depth; message length; multicore processors; network on chip architecture; on-chip-interconnection scheme; Clocks; Computer architecture; Conferences; Network topology; Object oriented modeling; Routing; Topology;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667883
