DocumentCode
1643638
Title
Chip package-system co-design
Author
Zheng, Ji ; Lee, Henry
Author_Institution
Apache Design Solutions, San Jose, CA, USA
fYear
2009
Firstpage
287
Lastpage
289
Abstract
To ensure that the system and chip work together, chip and system designers must provide the necessary models to one another during the design and verification stage. In this work, the issues in designing a chip-package-system are discussed and shown. Design techniques used to reduce power dissipation at 65 nm and below may negatively affect the system power supply. These issues can be avoided if chip designers provide a chip power model (CPM) to system designers.
Keywords
integrated circuit design; system-on-chip; chip package-system codesign; chip power model; system power supply; verification stage; Chip scale packaging; Impedance; Integrated circuit packaging; Logic design; Network synthesis; Power dissipation; Power supplies; Power system modeling; Timing; Voltage; BIST mode; Integrated Circuit Package; Power delivery network; Power-gating; Resonance; Scan mode; Target iImpedance; Voltage drop;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2009 International
Conference_Location
Busan
Print_ISBN
978-1-4244-5034-3
Electronic_ISBN
978-1-4244-5035-0
Type
conf
DOI
10.1109/SOCDC.2009.5423783
Filename
5423783
Link To Document