Title :
A new buried-gate VMOSFET with suppressed overlap capacitance and improved electrical characteristics
Author :
Kuo, Chih-Hao ; Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Fan, Yi-Hsuan
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
This study presents a new buried-gate vertical MOSFET (BGVMOS) with suppressed overlap capacitance and improved electrical characteristics due to its modified gate structure. According to the TCAD simulations, our proposed BGVMOS structure can gain reduced parasitic capacitances (27.11% Cgd and 37.53% Cgs at VDs = 1.0 V), improved drain saturation current, and free kink effect, in comparison to a conventional VMOS (CVMOS) structure. Most importantly, the reduced surface scattering in the BGVMOS helps improve the drain current and the transconductance mainly owing to the 1/4 circle gate scheme which is difficult task for a CVMOS transistor.
Keywords :
MOSFET; capacitance; surface scattering; technology CAD (electronics); BGVMOS; TCAD simulation; buried-gate vertical MOSFET; drain saturation current; kink effect; parasitic capacitance; suppressed overlap capacitance; surface scattering; transconductance; Capacitance; Couplings; Logic gates; Scattering; Threshold voltage; Transconductance; Transistors;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667887