Advanced static verification for SoC designs

After a design has been implemented in silicon, it is immensely difficult to debug any functional or silicon related problems. Hence, anything that can be done up-front at the RTL or gate-level to prevent errors will be extremely beneficial. So far, simulation-based dynamic verification has been relied upon heavily to verify the functionality of designs. In this paper, we summarize a number of static verification technologies - from simple RTL lint to sophisticated formal property verification - that can complement dynamic verification. These technologies can also help with low power verification and static timing analysis. Most importantly, they can target silicon related problems - such as clock domain crossing uncertainties, X-states, and uninitialized registers - that cannot be verified with dynamic simulation.