Title :
Experimental examination of physical model for direct tunneling current in unstressed/stressed ultrathin gate oxides
Author :
Takagi, S. ; Takayanagi, M. ; Toriumi, A.
Author_Institution :
Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
Physical mechanism of direct tunneling in unstressed and stressed gate oxides thinner than 5 nm is experimentally investigated. It is revealed that the direct tunneling current in an unstressed MOS (n/sup +/-poly Si/SiO/sub 2//Si substrates) structure has a strong bias polarity dependence, which is determined through the competing effects of tunneling probability and the number of tunneling carriers. It is also found that a leakage path allowing the flow of holes dominates SILC and leakage current after soft breakdown in stressed oxides less than 5 nm. This leakage path has the asymmetric carrier conduction property that current from the Si substrate is much larger than that from the n/sup +/-poly gate.
Keywords :
MIS structures; dielectric thin films; leakage currents; probability; semiconductor device breakdown; semiconductor device models; tunnelling; 5 nm; SILC; Si; Si-SiO/sub 2/-Si; asymmetric carrier conduction property; bias polarity dependence; direct tunneling current; leakage current; leakage path; n/sup +/-poly Si/SiO/sub 2//Si substrates; n/sup +/-poly gate; physical model; soft breakdown; stressed ultrathin gate oxides; tunneling carriers; tunneling probability; unstressed MOS structure; unstressed ultrathin gate oxides; Capacitance-voltage characteristics; Electric breakdown; Electrons; Laboratories; Large scale integration; Lead compounds; Leakage current; MOSFETs; Tunneling; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824193
