An efficient VLSI architecture and implementation of motion compensation for MPEG-4

An efficient VLSI architecture of motion compensation of MPEG-4 is presented in this paper. Aiming at the memory accessing problem of the motion compensation, three special methods were adopted. First, a novel interpolation pixel buffering mechanism and the corresponding parallel interpolation structure were proposed to save the buffering storage consumption of the interpolation pixels distinctly. Second, a modified method of motion vector decoding was adopted, which uses row buffer instead of storing the entire motion vectors of the whole frame, and can saves about 85% of the motion vector storage space. Third, method of hardware based unrestricted motion compensation was also discussed, using coordinate transformation to avoid pixel reproduction, can save both memory usage and memory accessing times. The design has been described by Verilog HDL and was implemented based on Field Programmable Gate Array (FPGA). Integrated with the motion compensation module, the whole MPEG-4 decoder can operate correctly.