Title :
Analysis of SRAM bit failure at high frequency operation
Author :
Yoshida, Y. ; Funayama, K. ; Nishida, A. ; Sekiguchi, T. ; Nakamura, K. ; Tomimatsu, S. ; Umemura, K. ; Yamanaka, T. ; Komori, K. ; Mitsui, Y. ; Ikeda, S.
Author_Institution :
Semicond. & Integrated Circuit Group, Hitachi Ltd., Tokyo, Japan
Abstract :
Careful analysis on SRAM bit failure at high frequency operation has been described. Using nano-prober technique, MOS characteristics of failure bit in actual memory cell had been measured directly. That confirmed drain current of PMOS was about one order smaller and threshold voltage was about 1 V higher than that of normal bit. Newly developed unique selective etching technique using hydrazine mixture showed these degradations ware caused by local gate depletion. And TEM observation showed PMOS gate poly-Si of failure bit had a huge grain. Minimizing grain size of gate poly-Si is found to be quite effective for improving drain current degradation and suppressing failure mode.
Keywords :
MOS memory circuits; SRAM chips; etching; failure analysis; grain size; transmission electron microscopy; PMOS memory cell; SRAM bit failure; Si; TEM; drain current; grain size; high frequency operation; hydrazine mixture; nanoprobe technique; polysilicon gate depletion; selective etching; threshold voltage; Electrical resistance measurement; Failure analysis; Frequency; Implants; MOS devices; Oxidation; Power supplies; Random access memory; Semiconductor device measurement; Voltage;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824196
