Analysis of SRAM bit failure at high frequency operation

Careful analysis on SRAM bit failure at high frequency operation has been described. Using nano-prober technique, MOS characteristics of failure bit in actual memory cell had been measured directly. That confirmed drain current of PMOS was about one order smaller and threshold voltage was about 1 V higher than that of normal bit. Newly developed unique selective etching technique using hydrazine mixture showed these degradations ware caused by local gate depletion. And TEM observation showed PMOS gate poly-Si of failure bit had a huge grain. Minimizing grain size of gate poly-Si is found to be quite effective for improving drain current degradation and suppressing failure mode.