Title :
A 1-V fully differential amplifier with buffered nested-Miller compensation
Author :
Shen, Meng-Hung ; Wang, Po-Min ; Wang, Li-Wen ; Huang, Po-Chiun
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
This paper presents a 1-V three-stage fully differential amplifier with buffered nested-Miller compensation. A transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero. In addition, a feedforward transconductance is used to enhance output large signal response. Using a standard 0.35-¿m CMOS technology, measurement results demonstrate that DC gain greater than 90dB, gain-bandwidth product of 4.57MHz, and phase margin of 55° is achieved with 100pF output loads. The settling time for a 1-Vpp step is 2¿s. All the circuits dissipate 110¿W under a single 1-V power supply.
Keywords :
CMOS integrated circuits; differential amplifiers; feedforward amplifiers; CMOS technology; buffered nested-Miller compensation; feedforward transconductance; power 110 muW; size 0.35 mum; three-stage fully differential amplifier; transconductance stage; voltage 1 V; CMOS technology; Capacitors; Circuit topology; Differential amplifiers; Feedback; Frequency; Low voltage; Poles and zeros; Stability; Transconductance; frequency compensation; low voltage; multi-stage amplifier;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423789
