Improved PMOSFET short-channel performance using ultra-shallow Si/sub 0.8/Ge/sub 0.2/ source/drain extensions

A new method of forming low-resistance, ultra-shallow p+ junctions for improved PMOSFET short-channel performance is presented. Ultra-shallow Si/sub 0.8/Ge/sub 0.2//Si heterojunctions self-aligned to the gate electrode are formed by Ge ion implantation. Afterwards, sidewall spacers are formed and a deep B implant is performed to form the deep source/drain (S/D) contact regions. Upon post-implant annealing, B diffuses rapidly in the ultra-shallow Si/sub 0.8/Ge/sub 0.2/ regions to form low resistivity extensions to the channel. As compared to a conventional LDD process, this new process provides significantly lower S/D-extension sheet resistance and superior PMOSFET short-channel behavior (drive current, threshold voltage roll-off, drain-induced barrier lowering). It eliminates the need for ultra-shallow B implantation as well as specialized rapid thermal annealing processes designed to minimize transient enhanced diffusion.