An FPGA implementation of a structured irregular LDPC decoder

Author

Cao, Zhigang ; Kang, Jingyu ; Fan, Pingyi

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

Volume

2

fYear

2005

Firstpage

1050

Abstract

In this paper, a code construction method of irregular low-density parity-check (LDPC) codes is presented, which facilitates the hardware implementation of belief propagation (BP) decoders and leads to low error floors as well. To verify the effectiveness of this construction, an FPGA-based decoder is designed and implemented, where a novel non-uniform quantization scheme for BP decoding is used, so that the performance loss compared to infinite-precision decoding is less than 0.1 dB. The decoding throughput of the decoder can reach as high as 50 Mbps.

Keywords

decoding; field programmable gate arrays; parity check codes; FPGA implementation; belief propagation; code construction method; field programmable gate array; infinite-precision decoding; low-density parity-check code; nonuniform quantization scheme; structured irregular LDPC decoder; Bit error rate; Computer architecture; Decoding; Field programmable gate arrays; Floors; Hardware; Parity check codes; Performance loss; Quantization; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2005. MAPE 2005. IEEE International Symposium on

Print_ISBN

0-7803-9128-4

Type

conf

DOI

10.1109/MAPE.2005.1618100

Filename

1618100