Incremental register placement for low power CTS

An incremental register placement algorithm within clock tree synthesis (CTS) is presented for low power system design. The method places registers together while generating the clock tree and hence is able to reduce clock tree wire-length. The increase in the logic wirelength is limited since the registers are moved within a small distance. The skew requirement of the clock tree can be strictly maintained as the limited register placement is integrated into the CTS algorithm. Experimental results show that the clock tree wirelength can be reduced by an average of 2.8% compared to the clock tree generated by BST/DME algorithm with a fanout factor of 2. The power consumption of this system is 1.1% less than that of a system with clock tree generated by BST/DME algorithm. Higher improvement can be achieved for higher fanout factors on a clock tree.