An instruction sequence assembling methodology for testing microprocessors

Hierarchically designed microprocessor-like VLSI circuits have complex data paths and complex embedded control machines to execute instructions. When a test pattern has to be applied to the input of an embedded module, determination of a sequence of instructions, which will apply this pattern and propagate the fault effects, is extremely diflcult. In this paper, we present a new methodology for automatic assembly of a sequence of instructions to satisfy the internal test goals. Combined with the previous equation-solving approach, this new high level ATPG methodology forms a complete solution for a variety of microprocessor-like circuits. This new approach has been implemented and experimented on three high level circuits. The results show that our approach is very effective in achieving complete automation for high level test generation.