Author :
Iguchi, M. ; Takewaki, T. ; Matsubara, Y. ; Kunimune, Y. ; Ito, N. ; Tsuchiya, Y. ; Matsui, T. ; Fujii, K. ; Motoyama, K. ; Sugai, K. ; Kubo, A. ; Suzuki, H. ; Tachibana, H. ; Nishizawa, A. ; Nakabeppu, K. ; Yamasaki, S. ; Yokogawa, S. ; Yamamoto, Y. ; Ku
Abstract :
A high performance 0.15-/spl mu/m CMOS logic device has been developed with full-0.56 /spl mu/m pitch 3-level copper (Cu) interconnects. The multi-level interconnect system consists of Cu single-damascene wiring in combination with a borderless W plug at a high aspect ratio of 3.0. A two-step Cu CMP method suppresses new wiring failures which are Cu ball generated from Cu polishing dross and side wall damage. A Cu spike into the W plug is prevented by optimizing the W plug formation process. The 0.28-/spl mu/m wide Cu wiring with a borderless W plug has advantages over Al-Cu wiring for electromigration (EM) reliability. We achieve a 23% reduction of RC delay of a ring oscillator with a loaded wiring length of 1.5 mm by reducing the wiring thickness by 300 nm.
Keywords :
CMOS logic circuits; chemical mechanical polishing; copper; delays; electromigration; integrated circuit interconnections; integrated circuit reliability; tungsten; 0.15 mum; 0.28 mum; 0.56 mum; Cu polishing dross; Cu single-damascene wiring; Cu spike prevention; Cu-W-TiN; RC delay; W plug formation process; borderless W plug; electromigration reliability; full-0.56 /spl mu/m pitch Cu multilevel interconnects; high aspect ratio; high performance 0.15-/spl mu/m CMOS logic device; loaded wiring length; ring oscillator; side wall damage; two-step Cu CMP method; wiring failure suppression; wiring thickness reduction; CMOS logic circuits; Copper; Corrosion; Plugs; Resists; Silicon compounds; Sputter etching; Sputtering; Tin; Wiring;
