A highly manufacturable 0.18 /spl mu/m generation logic technology

A 0.18 /spl mu/m generation logic technology has been developed with 0.14 /spl mu/m gate length transistors. Guidelines to suppress mechanical stress in shallow trench isolation are clearly described. Stable Co salicide process has been integrated with the combination of NO treated gate oxide and BF/sub 2/ source drain ion implantation. Amorphous Si with RTA is the key to control grain size and suppress large variation of drain current in small size transistors. Two kinds of metallization systems, aluminum with SiOF dielectrics and dual damascene Cu are developed in the same layout rule.