Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

Author

Shi, Yun ; Rassel, Robert M. ; Phelps, Richard A. ; Rainey, BethAnn ; Dunn, Jim ; Harame, David

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

2010

Firstpage

86

Lastpage

89

Abstract

In this paper, we discuss a method to extrapolate intrinsic and extrinsic R_on components for a JFET. The results provide the guideline to lower R_on, hence to achieve competitive “R_on vs. pinch off (V_off)” benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The optimized JFET demonstrates the 50% lowered R_on, low V_off of -2.75V, and high BVd_ss of 11V.

Keywords

BiCMOS integrated circuits; JFET circuits; circuit optimisation; elemental semiconductors; extrapolation; integrated circuit design; silicon; RESURF condition; RF/BiCMOS technology; Si; channel length scaling; extrapolation; optimization impacts; process variation; silicon JFET; size 180 nm; voltage -2.75 V; voltage 11 V; Doping; Electric breakdown; JFETs; Junctions; Logic gates; Optimization; Radio frequency; JFET; Ron; Voff; avalanche breakdown;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010 IEEE

Conference_Location

Austin, TX

ISSN

1088-9299

Print_ISBN

978-1-4244-8578-9

Type

conf

DOI

10.1109/BIPOL.2010.5667942

Filename

5667942