Title :
High performance 0.18 /spl mu/m SOI CMOS technology
Author :
Leobandung, E. ; Barth, E. ; Sherony, M. ; Lo, S.-H. ; Schulz, R. ; Chu, W. ; Khare, M. ; Sadana, D. ; Schepis, D. ; Boiam, R. ; Sleight, I. ; White, F. ; Assaderaghi, F. ; Moy, D. ; Biery, G. ; Goldblan, R. ; Chen, T.-C. ; Davari, B. ; Shahidi, G.
Author_Institution :
IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA
Abstract :
A 0.18 /spl mu/m SOI CMOS technology is presented. Key features in this technology are: more aggressive gate lithography (equivalent to 0.15 /spl mu/m half pitch generation) and devices than previously reported 0.18 /spl mu/m CMOS technology, low dose SIMOX SOI substrate, dual gate oxide, low /spl epsi/ BEOL insulator, and 7 layer copper metalization. Inverter delay of less than 6.5 ps has been achieved with this technology. A POWER4/sup TM/ test chip was built using the 0.18 /spl mu/m SOI technology and has demonstrated performance above 1 GHz.
Keywords :
CMOS digital integrated circuits; SIMOX; delays; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; isolation technology; photolithography; 0.18 micron; BEOL insulator; POWER4; SOI CMOS technology; dual gate oxide; gate lithography; half pitch generation; inverter delay; low dose SIMOX; metalization; CMOS technology; Capacitance; Circuits; Contamination; Implants; Lighting; Lithography; Shape; Silicon; Windows;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824243
