Title :
Demonstration of on-chip appended power amplifier for improved efficiency at low power region
Author :
Hyun-Min Park ; Sang-Hoon Cheon ; Jae-Woo Park ; Songcheol Hong
Author_Institution :
Dept. EECS, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
A new power amplifier topology which can achieve improved efficiency at power backoff region is demonstrated in this paper. In this topology, the output stage of the amplifier is appended with a secondary transistor in a parallel way through a 3-port interstage matching circuit and an impedance transforming network. By careful selection of the ratio of device active area, this appended transistor achieves earlier saturation at lower output power level than the output transistor, which is a basic requirement in achieving high efficiency. The power amplifier has been realized with InGaP/GaAs HBT technology and showed efficiency improvement of 81% at output power of 16.7 dBm. The proposed topology enables one-chip integration, hence is very attractive for portable communication terminals.
Keywords :
III-V semiconductors; MMIC power amplifiers; bipolar MMIC; bipolar analogue integrated circuits; gallium arsenide; gallium compounds; impedance convertors; impedance matching; indium compounds; 3-port interstage matching circuit; 81 percent; HBT technology; InGaP-GaAs; InGaP/GaAs; device active area; efficiency; impedance transforming network; low power region; on-chip appended power amplifier; one-chip integration; output power level; output stage; portable communication terminals; power backoff region; saturation; Circuit topology; Driver circuits; High power amplifiers; Impedance; Network topology; Operational amplifiers; Power amplifiers; Power generation; Power transistors; Switches;
Conference_Titel :
Microwave Symposium Digest, 2003 IEEE MTT-S International
Conference_Location :
Philadelphia, PA, USA
Print_ISBN :
0-7803-7695-1
DOI :
10.1109/MWSYM.2003.1212466
