Demonstration of on-chip appended power amplifier for improved efficiency at low power region

A new power amplifier topology which can achieve improved efficiency at power backoff region is demonstrated in this paper. In this topology, the output stage of the amplifier is appended with a secondary transistor in a parallel way through a 3-port interstage matching circuit and an impedance transforming network. By careful selection of the ratio of device active area, this appended transistor achieves earlier saturation at lower output power level than the output transistor, which is a basic requirement in achieving high efficiency. The power amplifier has been realized with InGaP/GaAs HBT technology and showed efficiency improvement of 81% at output power of 16.7 dBm. The proposed topology enables one-chip integration, hence is very attractive for portable communication terminals.