Title :
Architecture optimization for H.264/AVC propagate partial SAD engine in HDTV application
Author :
Huang, Yiqing ; Ikenaga, Takeshi
Author_Institution :
Syst. LSI Lab., Waseda Univ., Kitakyushu, Japan
Abstract :
This paper presents one compact propagate partial SAD (PPSAD) engine for H.264/AVC in HDTV application. Firstly, by using mode reduction technique, redundant registers in original PPSAD structure is removed. Secondly, circuit optimization is applied on the whole structure. Redundant adders within processing element (PE) and PE rows are removed. With TSMC 0.18 um technology under worst case conditions (1.62 V, 125°C), the proposed architecture can achieve 27.4% to 33.2% reduction of hardware and 11.7% saving in power consumption. When it is applied to parallel processing of HDTV 1080 p real-time encoder, about 10 k gates can be saved compared with previous design.
Keywords :
circuit optimisation; high definition television; logic design; video codecs; H.264/AVC; HDTV application; circuit optimization; mode reduction technique; parallel processing; propagate partial SAD engine; real time encoder; size 0.18 mum; temperature 125 C; voltage 1.62 V; Adders; Automatic voltage control; Circuit optimization; Engines; HDTV; Hardware; Laboratories; Large scale integration; Motion estimation; Parallel processing; H.264/AVC; Hardware Architecture; IME Engine;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423841
