Energy efficient fine-grain reconfigurable hardware

Author

Pournara, H. ; Kalenteridis, V. ; Pappas, I. ; Vassiliadis, N. ; Nikolaidis, S. ; Siskos, S. ; Soudris, D.J.

Author_Institution

Dept. of Phys., Aristotle Univ. of Thessaloniki, Greece

Volume

1

fYear

2004

Firstpage

209

Abstract

In this paper a novel energy efficient FPGA architecture was designed and simulated in STM 0.18μm CMOS technology. The parameters of the configurable logic block architecture have been determined in order to minimize energy consumption. Circuit level low power design techniques are also applied for further reducing energy consumption. In addition, an exploration for the optimum, in terms of energy, delay and area, interconnection routing switches size has been performed.

Keywords

CMOS logic circuits; delays; field programmable gate arrays; integrated circuit design; logic CAD; logic gates; reconfigurable architectures; 0.18 micron; FPGA architecture; STM 0.18μm CMOS technology; circuit level low power design techniques; configurable logic block architecture; delay; energy consumption minimization; energy efficiency; fine-grain reconfigurable hardware; gated block; interconnection routing switch size; CMOS logic circuits; CMOS technology; Circuit simulation; Delay; Energy consumption; Energy efficiency; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Reconfigurable logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 2004. MELECON 2004. Proceedings of the 12th IEEE Mediterranean

Print_ISBN

0-7803-8271-4

Type

conf

DOI

10.1109/MELCON.2004.1346810

Filename

1346810