Fast architecture exploration with hierarchical trace simulations

Design space of an embedded SoC with configurable IP cores is huge and the architecture exploration is thus time-consuming. Trace driven simulation is effective for simulation time reduction and various traces have been proposed to reuse simulation results for further explorations. However, the generation and access overheads of traces are significant and cannot be always ignored. This paper presents a systematic approach to integrate multiple traces to reduce the overall exploration time, where a simple model for exploration time estimation is provided for trace selection. In our experiments, 2~3-order speedup can be simply achieved once the traces are chosen appropriately.