GA2CO: Peak temperature estimation of VLSI circuits

With the continuing increase of chip density and the shrinkage of feature size of transistor in VLSI circuits, high temperature has become a concerned issue. High temperature not only decreases the functionality and reliability of chips, but also causes high package cost in order to cool down the system. For design consideration, one important issue related to temperature is how hot the chip may be. Thus, this paper investigates on the lower bound of peak temperature of a packaged chip and on the patterns that cause such bound. Two algorithms, Genetic Algorithm and Ant Colony Optimization, are applied for finding this lower bound of peak temperature. Experimental results show that the proposed approach obtains an average of 39.03% higher lower bound for ISCAS´85 combinational benchmarks and 6.80% for ISCAS´89 sequential benchmarks as compared to random approach under the TSMC 0.18 ¿m library.