A novel de-embedding technique for On-Wafer characterization of RF CMOS

Author

Loo, X.S. ; Yeo, K.S. ; Chew, K.W.J. ; Chan, L.H.K. ; Ong, S.N. ; Do, M.A. ; Boon, C.C.

Author_Institution

Sch. of Electr. Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

fYear

2009

Firstpage

29

Lastpage

32

Abstract

A novel de-embedding technique based on general fixture model is proposed to accurately de-embed the test fixture parasitic for characterization of RF CMOS at high frequency. The method is able to avoid over-de-embedding errors that exist in conventional techniques by utilizing three Thru structures of zero length and one Open dummy test structures for accurate extraction of fixture parasitic. The de-embedding result is verified with Thru line replaced as intrinsic device and has been shown matching closer to the actual intrinsic Thru line than other compared techniques for frequency of up to 50 GHz.

Keywords

CMOS integrated circuits; radiofrequency integrated circuits; Open dummy test structures; RF CMOS; de-embedding technique; fixture parasitic; general fixture model; intrinsic Thru line; on-wafer characterization; CMOS technology; Circuit testing; Fixtures; Geometry; Industrial electronics; Integrated circuit interconnections; Radio frequency; Scattering parameters; Semiconductor device modeling; Silicon; De-embedding; Fixture parasitic; High frequency characterization; RF CMOS; Scattering parameters;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2009 International

Conference_Location

Busan

Print_ISBN

978-1-4244-5034-3

Electronic_ISBN

978-1-4244-5035-0

Type

conf

DOI

10.1109/SOCDC.2009.5423849

Filename

5423849