• DocumentCode
    1645476
  • Title

    Architectural-level prediction of interconnect wirelength and fanout

  • Author

    Jeong, Kwangok ; Kahng, Andrew B. ; Samadi, Kambiz

  • Author_Institution
    ECE Dept., UC San Diego, La Jolla, CA, USA
  • fYear
    2009
  • Firstpage
    53
  • Lastpage
    56
  • Abstract
    This paper proposes accurate architectural-level interconnect wirelength and fan-out models. Existing models are based on Rent´s rule and fail to capture the impact of microarchitectural and implementation parameters. Hence, significant deviation is observed when validated against implementation data, i.e., up to 79% (22%) in total wirelength (average fanout). Our proposed models both enable architectural-level prediction of interconnect wirelength and fanout, and show significant accuracy improvement vs. existing models with respect to layout data.
  • Keywords
    VLSI; integrated circuit layout; integrated circuit modelling; VLSI; accuracy improvement; architectural-level interconnect wirelength; fan-out models; implementation parameters; layout data; microarchitectural parameters; Equations; Frequency estimation; Information analysis; Microarchitecture; Pins; Power system interconnection; Power system modeling; Predictive models; Routing; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2009 International
  • Conference_Location
    Busan
  • Print_ISBN
    978-1-4244-5034-3
  • Electronic_ISBN
    978-1-4244-5035-0
  • Type

    conf

  • DOI
    10.1109/SOCDC.2009.5423853
  • Filename
    5423853