Integrated CMOS imager for pattern recognition

Author

Sarje, Anshu ; Satsangi, Sharad ; Skipwith, Armstard C. ; Chiang, Jui-Ping ; Abshire, Pamela

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD

fYear

2008

Firstpage

217

Lastpage

220

Abstract

This paper presents an analog CMOS architecture for on-chip pattern recognition. The system comprises a CMOS imager in the front end followed by low power computation circuitry for determining a match between the captured image and image patterns stored in on-chip memory. The imager has a programmable kernel selector and correlated double sampling circuit for suppression of fixed pattern noise. The closeness of a successful match can be controlled by an input bias current. The prototype with a 6 times 6 pixel array in a 0.5 mum CMOS process is being implemented. This chip can be used for applications requiring dedicated pattern recognition.

Keywords

CMOS analogue integrated circuits; CMOS image sensors; VLSI; biomimetics; image matching; low-power electronics; neurophysiology; VLSI pattern recognition; analog CMOS architecture; correlated double sampling circuit; fixed pattern noise suppression; image capture; image patterns; integrated CMOS imager; low power computation circuitry; neuromorphic system; on-chip memory; on-chip pattern recognition; programmable kernel selector; CMOS memory circuits; CMOS process; Circuit noise; Computer architecture; Image sampling; Kernel; Pattern matching; Pattern recognition; Prototypes; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Biomedical Circuits and Systems Conference, 2008. BioCAS 2008. IEEE

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-2878-6

Electronic_ISBN

978-1-4244-2879-3

Type

conf

DOI

10.1109/BIOCAS.2008.4696913

Filename

4696913