Fixing lithography hotspots on routing without timing discrepancy

This paper is for practical design methodology on placement & route (P&R) to fix lithography hotspots. This methodology for block and chip level design consists of lithography simulation and metal routing on physical layout. The lithography simulation as design for manufacturability is very important solution in 45 nm technology and below because of limits of lithography wavelength related to minimum feature size. Therefore, solutions to fix lithography hotspots in layout, which may cause systematic defects in process, are needed to make sure lithography patterning layout. However, some solutions may seriously impact timing characteristics which can lead to engineering change order as design overhead. One of the solutions to maximize fixing coverage and minimize overhead is proposed in this work. As implementation and integration of chip level design flow, the fixing coverage of lithography hotspots is maximum 78% of real hotspots and the timing discrepancy due to fixing is less than 5 ps.