Title :
High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O
Author :
Lei, Cheok-Teng ; Seng-Pan, U. ; Martins, R.P.
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Macau, Macau, China
Abstract :
A new level converter aimed at ultra-low core voltage and wide range I/O voltage is designed using deep submicron process with standard MOS transistor without adding extra mask or process step. Simulation results demonstrate the performance improvement of the proposed level converter which can convert high-speed clock signals from 0.6-V to 3.3-V I/O interface within 0.5ns and maintain 50:53 of duty ratio.
Keywords :
MOSFET; large scale integration; low-power electronics; power convertors; I/O interface; deep submicron process; high-speed clock signals; high-speed robust level converter; standard MOS transistor; ultra-low core voltage; ultra-low power LSI; voltage 0.6 V to 3.3 V; wide range I/O voltage; Circuits; Clocks; Digital audio players; Diodes; Feedback; Low voltage; MOSFETs; Noise robustness; Signal design; Threshold voltage;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423870
