Static frequency dividers up to 133GHz in SiGe:C bipolar technology

This paper presents current-mode logic (CML) and emitter-coupled logic (ECL) static frequency dividers in a SiGe:C bipolar process with a cut-off frequency f_T of 230 GHz. Speed/power trade-offs are investigated by comparing three different circuit versions. Each contains two master-slave flipflops to achieve a divide ratio of four. The first version uses current-mode logic flip-flops and achieves a maximum operating frequency of 87 GHz at a power consumption of only 14 mW in the first flip-flop. Two versions use emitter-coupled logic with one and two emitter follower stages in the feedback path, respectively. The low-power divider with one emitter follower operates up to 105 GHz while the second circuit achieves a maximum operating frequency of 133 GHz. The power consumption in the first flip-flop is 51 mW and 210 mW, respectively. The circuits use standard flip-flops without speed-enhancement techniques, such as split load resistors, inductive peaking, or asymmetric latches.