DocumentCode
1646047
Title
VLSI array processors: designs and applications
Author
Kung, S.Y.
Author_Institution
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fYear
1988
Firstpage
313
Abstract
The key issues in designing an algorithm-oriented array processor are addressed in this tutorial. The author discusses how to express the parallelism and description of the space-time activities associated with a parallel algorithm, how to systematically derive a VLSI array hardware design, and how to apply the methodology to image/vision processing applications. The applications include 2-D convolution for edge detection, rank order filter for noise removal and artificial neural nets for associative classification
Keywords
VLSI; computerised picture processing; microprocessor chips; parallel processing; 2-D convolution; VLSI array processors; algorithm-oriented array processor; artificial neural nets; associative classification; edge detection; hardware design; image/vision processing applications; noise removal; parallelism; rank order filter; space-time activities; Algorithm design and analysis; Hardware; Image processing; Parallel architectures; Parallel processing; Pipeline processing; Process design; Signal processing; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo
Type
conf
DOI
10.1109/ISCAS.1988.14929
Filename
14929
Link To Document