DFT for achieving hybrid transiton delay fault test with Reduced Pin Count Testing

Author

Son, Changwon ; Ahn, Seongyong ; Kang, Sungho

Author_Institution

Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

2009

Firstpage

128

Lastpage

132

Abstract

This paper presents a new DFT (design-for-testability) for achieving the hybrid TDF (transition delay fault) test with RPCT (reduced pin count testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.

Keywords

boundary scan testing; design for testability; fault diagnosis; logic testing; ISCAS89 benchmark circuits; ITC99 benchmark circuits; at-speed delay test; boundary scan structure; design-for-testability; hardware overhead; hybrid transiton delay fault test; reduced pin count testing; stuck-at test; Benchmark testing; Circuit faults; Circuit testing; Costs; Delay; Design for testability; Frequency; Hardware; Performance evaluation; Throughput; IEEE 1149.1; Transition delay test; design-for-testability (DFT); reduced pin count testing (RPCT);

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2009 International

Conference_Location

Busan

Print_ISBN

978-1-4244-5034-3

Electronic_ISBN

978-1-4244-5035-0

Type

conf

DOI

10.1109/SOCDC.2009.5423888

Filename

5423888