DocumentCode :
1646406
Title :
Design and analysis of video parallel processing on a hierachical multiprocessor system on FPGA
Author :
Li, Da ; Hou, Yibin ; Huang, Zhangqin ; Xiao, Chunhua
Author_Institution :
School of Electronics and Information Engineering, Xi´´an Jiaotong University, Xi´´an, P.R. China, Embedded Software and Systems Instiute, Beijing University of Technology (BJUT), Beijing, P.R. China
fYear :
2011
Firstpage :
1
Lastpage :
4
Abstract :
Recently there has been a growing interest in models and methods targeted towards the design of video stream parallel processing, and the applications tend to be highly bursty and dependent parallel. As a result, the most existing models are not suitable for dealing with such system design. In this paper, we present an Event Count Model (ECM) to capturing the timing properties of video stream processing in the hierarchical system structure; and we also use Continuous Markov Chain modeling and high level colored time Petri net to describe the multiprocessor system architecture and co-design of software and hardware. Simulations of the asynchronous and concurrent interactions of system, and formal co-verification approach with CPN Tools is proposed and a case of h.264 encoder on MPSoC is used for illustrate these explanations.
Keywords :
Analytical models; Computer architecture; Embedded systems; Hardware; Streaming media; Timing; Multiprocessor System; Petri net; embedded system design; modeling and analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
E -Business and E -Government (ICEE), 2011 International Conference on
Conference_Location :
Shanghai, China
Print_ISBN :
978-1-4244-8691-5
Type :
conf
DOI :
10.1109/ICEBEG.2011.5882114
Filename :
5882114
Link To Document :
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