Title :
Simulating fixed point systems
Author :
Thorlby, J.P. ; Burr, A.G.
Author_Institution :
Dept. of Electron., York Univ., UK
fDate :
9/28/1993 12:00:00 AM
Abstract :
This paper describes a technique which can be used for simulating fixed point arithmetic using `standard´ SPW rather than the hardware design system (HDS). The method is relatively quick in system development and does not require the purchase of HDS. The drawback is that the extra features of HDS are not present, such as VHDL generation. The technique is specifically developed for the Q15 format as used in the Texas Instruments TMS320C25 DSP chip. It is illustrated by simulation of a fixed point FFT algorithm
Keywords :
digital arithmetic; digital signal processing chips; digital simulation; fast Fourier transforms; FFT algorithm; Q15 format; TMS320C25 DSP chip; fixed point arithmetic;
Conference_Titel :
Communications Simulation and Modelling Techniques, IEE Colloquium on
Conference_Location :
York
