On-chip transaction level debug support for system-on-chips

This paper introduces a method to raise the debug abstraction level of communications to transaction level in post-silicon verification. The method is based on on-chip instrumentation using formal specifications of the on-chip bus communication protocols. Furthermore, we present a method for automatic analysis of extracted transactions to find potential erroneous transaction sequences. The post analysis method searches for certain patterns to find potential problems such as deadlock and race. To show the feasibility of the method, it is applied to a number of on chip buses. It is shown that the area overhead of the method is very low and it is effective to locate bugs.