Title :
Real-Time power management for a multi-performance processor
Author_Institution :
Syst. LSI Res. Center, Kyushu Univ., Fukuoka, Japan
Abstract :
This paper presents an energy efficient embedded processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded real-time system design. The processor consists of multiple same-ISA PE (processing element) cores and a selective set-associative cache memory. The PE-cores differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating. The major advantage over the DVS processors is a small overhead for changing its performance. Our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for each voltage transition. Our processor makes it possible to use the DVS control in embedded real-time systems and to perform more sophisticated dynamic power management.
Keywords :
embedded systems; integrated circuit design; microprocessor chips; multiprocessing systems; power aware computing; clock gating; dynamic voltage scaling processors; embedded real-time system design; energy consumptions; energy efficient embedded processor; multiperformance processor; processing element cores; real-time power management; selective set-associative cache memory; signal gating; Cache memory; Clocks; Control systems; Dynamic voltage scaling; Energy consumption; Energy efficiency; Energy management; Power system management; Real time systems; Voltage control; Embedded systems; Low-power design; Microprocessor; Real-time systems;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423892
