1646588

An Evaluation of I/sub DDQ/ Versus Conventional Testing for CMOS Sea-of-Gate IC´s

Sawada, K. ; Kayano, S.

1995

158

Automatic test pattern generation; CMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit testing; Logic circuits; Logic design; Logic testing; Paper technology; Semiconductor device measurement;

English

ieee

Test Conference, 1992. Proceedings., International

Baltimore, MD

1089-3539

0-7803-0760-7

conf

10.1109/TEST.1992.527816

527816