DocumentCode
1646625
Title
Very high performance 50 nm CMOS at low temperature
Author
Wind, S.J. ; Shi, L. ; Lee, K.-L. ; Roy, R.A. ; Zhang, Y. ; Sikorski, E. ; Kozlowski, P. ; D´Emic, C. ; Bucchignano, J.J. ; Wann, H.-J. ; Viswanathan, R.G. ; Cai, J. ; Taur, Y.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1999
Firstpage
928
Lastpage
930
Abstract
In this work, we present very high performance CMOS devices with 50 nm channel lengths on 1.7 nm gate oxide, suitable for low temperature operation. Saturation transconductances of 1380 mS/mm for nMOSFETs and 523 mS/mm for pMOSFETs are achieved at -200 /spl deg/C. At the same temperature, I/sub on/ for a 1.2 V supply is 1.2 mA//spl mu/m for nMOSFET, and 0.5 mA//spl mu/m for pMOSFET, respectively, with I/sub off/ of both devices on the order of 10 nA//spl mu/m. A delay of 6.4 ps per stage at 1.5 V is measured at -100 /spl deg/C for a 101-stage CMOS ring oscillator. The delay of the same ring oscillator at room temperature is 8.2 ps per stage. These represent the highest CMOS performance figures reported to date.
Keywords
CMOS integrated circuits; MOSFET; cryogenic electronics; -100 C; -200 C; 1.2 V; 1.5 V; 50 nm; CMOS device; low temperature operation; nMOSFET; pMOSFET; ring oscillator; saturation transconductance; Delay; MOS devices; MOSFETs; Proposals; Ring oscillators; Temperature control; Temperature sensors; Threshold voltage; Transconductance; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location
Washington, DC, USA
Print_ISBN
0-7803-5410-9
Type
conf
DOI
10.1109/IEDM.1999.824301
Filename
824301
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