Compressive acquisition CMOS image sensor using on-line sorting scheme

In this paper, we propose a compact block-based compressive acquisition CMOS image sensors. The overall image is decomposed into blocks. The proposed design reorders the raw captured pixel values within each block, only recording the brightest pixel value and the darkest pixel value for each block using full precision (typically 8-bit). During reconstruction, block models are built to model the value distribution within one block. As in a digital pixel sensor (DPS) array the pixel data are naturally ordered (from the brightest to the darkest pixel), the block-level hardware overload while implementing the proposed scheme is very low. The proposed scheme enables reduced memory requirement, and hence enabling significant silicon area saving. The compression performance and image quality of the proposed algorithm are thoroughly analyzed for different block sizes and a mathematical model is subsequently derived. Simulation result shows that the proposed algorithm enables more than 80% pixel-level memory reduction at a PSNR level around 23 dB and using 1BPP.