Title :
Strategy to Detect Bug in Pre-silicon Phase
Author :
See, Mary Yeoh Siaw
Author_Institution :
Penang Design Center, Intel Corp., Georgetown, Malaysia
Abstract :
Bugs still escape to post-silicon despite huge effort has been put into validating the design in pre-silicon phase. This could cost an immediate stepping while some other bugs may have a software work around. Running more tests may still miss the bugs. Therefore it is necessary to have an effective strategy during pre-silicon phase. This paper will present a strategy to derive the test points from the validation objective, and set the domain to test based on the micro-architecture, before entering simulation environment. This strategy utilized coverage based validation (CVB), with test points and domain coded as coverage points, while the test generator directed the transactions into the domain to test. This provides a comprehensive validation coverage to the design under test.
Keywords :
elemental semiconductors; integrated circuit design; program debugging; program testing; silicon; system-on-chip; Si; SoC design; bug detection strategy; coverage based validation strategy; presilicon phase; system-on-chip; test generator; Analytical models; Circuit testing; Computer bugs; Costs; Cryptography; Logic design; Logic testing; Microarchitecture; Phase detection; Registers; RTL; pre-silicon; validation;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423900
