Novel architecture for inverse mix columns for AES using ancient Vedic Mathematics on FPGA

With the ever increasing demand for secure transactions in banking and also in mail delivery systems, encryption and decryption using cryptography plays a very important role. Nowadays, with 90% of secure transactions occurring on smart phones and other hand-held devices, a low on-chip area and a high speed algorithm to perform the same becomes the need for the day. In order to meet this requirement, several algorithms have been designed and implemented in the past, but each of these algorithms possess their own shortcomings with respect to an ASIC or an FPGA implementation. In this paper, we propose a novel and area efficient architecture for performing the mix columns & inverse mix columns operation, which is the major operation in the Advanced Encryption Standard (AES) method of cryptography. We perform the same using ancient Vedic Mathematics techniques. The cryptographic unit involving mix columns & inverse mix columns for AES was designed and implemented on a Xilinx Spartan 3e series of FPGA. A 100% area efficiency and a 2 times increase in speed was achieved by the novel algorithm, in comparison with two other popular implementations of the same.