DocumentCode :
1646815
Title :
Cost/performance tradeoff of n-select square root implementations
Author :
Chu, Wanming ; Li, Yamin
Author_Institution :
Lab. of Comput. Archit., Aizu Univ., Aizu-Wakamatsu, Japan
fYear :
2000
fDate :
6/22/1905 12:00:00 AM
Firstpage :
9
Lastpage :
16
Abstract :
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper we present four low-cost high-performance fully-pipelined n-select implementations (nS-Root) based on a non-restoring-remainder square root algorithm. The nS-Root uses a parallel array of carry-save adders (CSAs). For a square root bit calculation, a CSA is used once. This means that the calculations can be fully pipelined. It also uses the n-way root-select technique to speedup the square root calculation. The cost/performance evaluation shows that n=2 or n=2.5 is a suitable solution for designing a high-speed fully pipelined square root unit while keeping the low-cost
Keywords :
pipeline arithmetic; cost/performance evaluation; non-restoring-remainder square root; pipelined; pipelined square root unit; square-root units; Computer applications; Computer architecture; Cost accounting; High performance computing; Iterative algorithms; Laboratories; Newton method; Parallel processing; Pipelines; Production;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture Conference, 2000. ACAC 2000. 5th Australasian
Conference_Location :
Canberra, ACT
Print_ISBN :
0-7695-0512-0
Type :
conf
DOI :
10.1109/ACAC.2000.824317
Filename :
824317
Link To Document :
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