Custom digital cell generation flow for 65nm processes

Process technologies generate increasing challenges for layout efficiency at the 65nm process. This has increased the reliance on standard cell library development in order to simultaneously meet the demand of today´s tight design schedules. However due to IP-specific design constraints, customized logic cells are frequently necessary to achieve design closure. We explore a design flow that efficiently characterizes a standard cell for power, timing and reliability considerations within custom design, and further synthesizes promising circuit alternatives using a spec-driven optimization approach through transistor level sizing. This methodology provides a unique ability for determining tradeoffs between physical design and circuit design challenges.