Title :
On-chip power noise measurements of high-frequency CMOS digital circuits
Author :
Matsuno, Tetsuro ; Nagata, Makoto
Author_Institution :
Dept. of Comput. Sci. & Syst. Eng., Kobe Univ., Kobe, Japan
Abstract :
On-chip power and substrate noise measurements were performed on shift registers in a 90-nm CMOS technology, with operating frequencies ranging from 100 MHz up to 1.2 GHz. Combined on-chip digitization and off-chip timing generation achieves the effective measurement bandwidth as high as 1.3 GHz. It was experimentally observed that dynamic components of power noise decrease for the higher operating frequencies.
Keywords :
CMOS digital integrated circuits; electric noise measurement; integrated circuit noise; integrated circuit testing; shift registers; system-on-chip; CMOS digital circuits; frequency 100 MHz to 1.2 GHz; off-chip timing generation; on-chip digitization; on-chip power noise measurement; shift registers; size 90 nm; substrate noise measurement; system-on-chip; CMOS digital integrated circuits; Digital circuits; Noise measurement;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423904
